• 1
• 0
• 0

付浩东/RAM_FIFO

Verilog实验单端口RAM、简单双端口RAM、真双端口RAM、同步FIFO和异步FIFO模块。能够完全替代Xilinx官方IP核。软件版本：Vivado2018.3。

• 1
• 0
• 0

付浩东/1002

• 1
• 0
• 20

付浩东/hbird-sdk forked from RISCV-MCU/hbird-sdk

HummingBird RISC-V Software Development Kit

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• 0
• 69

付浩东/e203_hbirdv2 forked from RISCV-MCU/e203_hbirdv2

The Ultra-Low Power RISC-V Core