• 3
• 0
• 0

chisel

Chisel: A Modern Hardware Design Language

• 3
• 0
• 0

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

• 3
• 0
• 0

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linu...

• 3
• 0
• 0

omnixtend

OmniXtend cache coherence protocol

• 3
• 0
• 0

fpga-interchange-tests

Repository to run extensive tests on the FPGA interchange format

• 3
• 0
• 0

riscv-fw-infrastructure

SDK Firmware infrastructure, contain RTOS Abstraction Layer, demos, SweRV Processor Support Package, and more ...

• 3
• 0
• 0

f4pga-xc-fasm2bels

Library to convert a FASM file into BELs importable into Vivado.

• 3
• 0
• 0

f4pga-rr-graph

Collection of Routing Resources Graph (RR Graph) libraries for VPR

• 3
• 0
• 0

f4pga-database-visualizer

• 3
• 0
• 0

caliptra-rtl

HW Design Collateral for Caliptra RoT IP

• 3
• 0
• 0

rocket-chip

Rocket Chip Generator

• 3
• 0
• 0

verible-linter-action

Automatic SystemVerilog linting in github actions with the help of Verible

• 2
• 0
• 0

VeeR-EL2-Tock

• 3
• 0
• 0

chisel3

Chisel: A Modern Hardware Design Language

• 2
• 0
• 0

i3c-core

• 2
• 0
• 0

caliptra-ss

HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.

• 2
• 0
• 0

adams-bridge

Post-Quantum Cryptography IP Core (Crystals-Dilithium)

• 3
• 0
• 0

yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

• 3
• 0
• 0

vtr-xml-utils

• 3
• 0
• 0

UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor an...